1. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the same, and more particularly to a semiconductor package with a light, thin, simple and compact structure having a size reduced to the size of its semiconductor chip and input/output terminals arranged in the form of an area array in either case using a semiconductor chip having bond pads arranged on end portions of the chip or a semiconductor chip having bond pads arranged on the central portion of the chip, thereby achieving an improvement in integration degree and performance of the package. Also, the present invention relates to a method for fabricating such a semiconductor package.
2. Description of the Prior Art
Generally, semiconductor packages are classified into resin sealed packages, TCP packages, glass sealed packages and metal sealed packages. Such semiconductor packages are also classified into insertion type semiconductor packages and surface mounting type semiconductor packages in accordance with their chip mounting structures. The representative of insertion type semiconductor packages includes dual in-line packages (DIP) and pin grid array (PGA) packages. On the other hand, the representative of surface mounting type semiconductor packages include quad flat packages (QFP), plastic leaded chip carrier (PLCC) packages, ceramic leaded chip carrier (CLCC) packages, and ball grid array (BGA) packages.
Recently, the surface mounting type semiconductor packages have been widely used as compared to the insertion type semiconductor packages in order to obtain an increased degree of mounting elements on printed circuit boards as electronic appliances have a compact structure. Conventional package structures will now be described in conjunction with FIGS. 1A and 1B respectively illustrating a QFP package and a BGA package.
FIG. 1A shows a conventional QFP package. As shown in FIG. 1A, the QFP package includes a semiconductor chip 1 having an integrated electronic circuit. The semiconductor chip 1 is attached to a mounting plate 2 by means of an epoxy resin 3. The package also includes a plurality of leads 7 adapted to transmit a signal from the semiconductor chip 1 to the outside, a plurality of wires 4 respectively connecting the leads 7 to the semiconductor chip 1, and a sealant 5 adapted to encapsulate the semiconductor chip 1 and peripheral elements, thereby protecting them from external oxidation and erosion.
In such a conventional QFP package having the above-mentioned structure, signals output from the semiconductor chip 1 are transmitted to the leads 7 via the wires 4, respectively. The signals transmitted to the leads 7 are then sent to peripheral devices via a mother board to which the leads 7 are coupled. On the other hand, transmission of signals generated from the peripheral devices to the semiconductor chip 1 is carried out in a manner reverse to the above-mentioned manner.
However, such a QFP package has a technical difficulty in reducing the interval between adjacent pins. The recent trend to fabricate semiconductor chips having a high performance results in an increase in the number of pins. In order to contain such an increased number of pins, the QFP package becomes bulky. This brings an adverse effect on the compactness of the package.
BGA packages are known to solve a technical requirement for an increase in the number of pins. Such BGA packages have input/output means comprising solder balls bonded to one package surface. By virtue of such solder balls, BGA packages can contain an increased number of input/output signals as compared to QFP packages while having a reduced size. Referring to FIG. 1B, an example of such BGA packages is illustrated. As shown in FIG. 1B, the BGA package includes a circuit board 8 having a circuit pattern 8a formed on the upper surface of the circuit board 8 and a solder mask 8b coated on the circuit pattern 8a to protect the circuit pattern 8a. A semiconductor chip 1 is attached to the central portion of the upper surface of the circuit board 8. A plurality of wires 4 are connected between the semiconductor chip 1 and the circuit pattern 8a of the circuit board 8 so that signals can be transmitted between the semiconductor chip 1 and circuit pattern 8a. The BGA package also includes a plurality of solder balls 6 bonded to the circuit pattern 8a of the circuit board 8 and adapted to transmit signals from the package to the outside, and a sealant 5 adapted to encapsulate the semiconductor chip 1 and peripheral elements, thereby protecting them from external oxidation and erosion.
In such a conventional BGA package having the above-mentioned structure, signals output from the semiconductor chip 1 are transmitted to the circuit pattern 8a via the wires 4, respectively. The signals transmitted to the circuit pattern 8a are then sent to a mother board via the solder balls 6 and then transmitted to peripheral devices. On the other hand, transmission of signals generated from the peripheral devices to the semiconductor chip 1 is carried out in a manner reverse to the above-mentioned manner.
However, such a BGA package has a size corresponding to several times the size of the semiconductor chip contained therein. As a result, the BGA package has a limitation in reducing the size of electronic appliances using it. Moreover, the circuit board of the BGA package is expensive, thereby resulting in an increase in cost of final products. In particular, moisture may penetrate into the circuit board, thereby resulting in generation of cracks.